1. Field of the Invention
The present invention relates to a multi-processor system. Specifically, the present invention relates to a multi-processor system that monitors the state of a load in memory access and distributes a load in memory access based on the monitoring so as to improve throughput of the entire multi-processor system, and a memory access load distributing method therefor.
2. Description of the Related Art
Many computer systems with high performance have adapted a multi-processor system mounted with a plurality of processors (CPUs) for improving total throughput. Many multi-processor systems adapts a system using a plurality of multi-chip packages (MCP) mounted with processors memories for eliminating the amount of hardware in a bus controlling unit and a bus signal line. In the multi-chip package, difference in memory access latency occurs due to the structure of the multi-chip package.
For example, in the multi-processor system of the NUMA (Non-Uniform Memory Access, Non-Uniform Memory Architecture), access latency from a CPU to an address space and access latency from the CPU to another address space are different. That is to say, in such a multi-processor system, an address space with a short latency and an address space with a long latency for the same CPU exist.
Generally, in the NUMA architecture, these two latencies differ in their performance by from threefold to fivefold. Japanese Patent Laid-Open Publication No. JP2005-216053A discloses a technique for converting a reallocated address of a memory in consideration of the usage of a memory in the system with at least two memories. Generally, the operating system (OS), however, does not control with consideration of physical relationship between a CPU and a memory, thus, it is hard to perform CPU allocation and memory allocation in consideration of memory access latency. Therefore, some resource allocation may cause memory access from a processor converges concentrate to an address space with a long latency, resulting in lower performance of the entire multi-processor system.